Hi VLSI Readers, welcome to the blog, as we’ve completed the Drain current. We’ll move to next topic of Body Biasing.
The word body biasing itself tells us that we’re biasing the body rather than tying it up with source. We’re taking example of NMOS here.
What happens if we don’t ?
We apply positive voltage to body i.e. VBS = +ve
It will reduce the Vt & help the Vg to overcome the Vt quickly and create the channel quick.
In other way , Gate voltage Vg has to do less work to invert the surface or to create the channel.
Its Impact :
Less gate voltage needs to be applied.
The device is faster.
Less delay.
Id (Drain current increases).
Leakage increases.
Setup time improves.
Hold time worsens.
What if we apply negative voltage to body. i.e. VBS = -ve
The negative voltage will make the Vt increase.
It will make the gate voltage Vg to put more effort for creating a channel or to cross the threshold voltage.
Its impact:
Vg needs to put more effort.
Device is slower.
More delay.
Id (Drain current reduces).
Leakage decreases.
Setup time worsens.
Hold time improves.
Note: Forward body bias is limited in bulk CMOS because excessive positive body bias can forward-bias the body-source PN junction, causing unwanted current flow.
Now the real question is : Do we use this to our advantage in advance nodes ?
Think about it, the answer will be in next blog
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